PRES=CLK_1, CSS=SLOW_CLK, MDIV=EQ_PCK
Master Clock Register
| CSS | Master Clock Source Selection 0 (SLOW_CLK): Slow Clock is selected 1 (MAIN_CLK): Main Clock is selected 2 (PLLA_CLK): PLLA Clock is selected 3 (UPLL_CLK): Divided UPLL Clock is selected |
| PRES | Processor Clock Prescaler 0 (CLK_1): Selected clock 1 (CLK_2): Selected clock divided by 2 2 (CLK_4): Selected clock divided by 4 3 (CLK_8): Selected clock divided by 8 4 (CLK_16): Selected clock divided by 16 5 (CLK_32): Selected clock divided by 32 6 (CLK_64): Selected clock divided by 64 7 (CLK_3): Selected clock divided by 3 |
| MDIV | Master Clock Division 0 (EQ_PCK): Master Clock is Prescaler Output Clock divided by 1. 1 (PCK_DIV2): Master Clock is Prescaler Output Clock divided by 2. 2 (PCK_DIV4): Master Clock is Prescaler Output Clock divided by 4. 3 (PCK_DIV3): Master Clock is Prescaler Output Clock divided by 3. |
| UPLLDIV2 | UPLL Divider by 2 |